1. Field of the Invention
The present invention relates to a switching power supply apparatus, more particularly, it concerns a switching power supply apparatus using the RCC (Ringing Choke Converter) system.
2. Description of the Related Art
Generally, equipment such as a VTR and a facsimile requires a stable DC voltage, and a switching power supply apparatus comprising an RCC system which is relatively simple in structure and highly efficient is extensively used to supply the stable DC voltage from the commercial AC power source.
FIG. 7 illustrates a switching power supply apparatus of the conventional RCC system. In FIG. 7, a switching power supply apparatus 1 comprises an input circuit 2, a DC--DC converter circuit 3, a voltage detection circuit 4, and a control circuit 5.
The input circuit 2 comprises a diode bridge DB for rectification, a fuse F and line filter LF provided between the AC power source and an input end of the diode bridge DB, and a smoothing capacitor C1 provided in parallel to an output end of the diode bridge DB.
The DC--DC converter circuit 3 comprises a transformer T having a primary winding N1, a secondary winding N2 of opposite polarity to the primary winding N1 and a feedback winding Nb of the same polarity as the primary winding N1, a switching element FET Q1 connected in series with the primary winding N1, a starting resistor R1 connected between one end of the primary winding N1 and the gate control terminal of the FET Q1, a diode D1 for rectification connected in series with the secondary winding N2, and a smoothing capacitor C4 connected between a cathode of the diode D1 and one end of the secondary winding N2.
The voltage detection circuit 4 provided on the output side of the DC--DC converter circuit 3 comprises a resistor R5, a light-emitting diode PD on the light emission side of a photo coupler PC, a shunt regulator Sr, and resistors R6,R7. The resistor R5, the light-emitting diode PD, and the shunt regulator Sr are connected in series, and provided in parallel to the capacitor C4 of the DC--DC converter circuit 3. The resistors R6 and R7 are also connected in series, and provided in parallel to the capacitor C4. A common connection of the resistor R6 to the resistor R7 is connected to the control terminal of the shunt regulator Sr.
The control circuit 5 comprises a resistor Rb and a capacitor C3 connected in series between one end of the feedback winding Nb and a gate of the FET Q1, a transistor Q2 connected between the gate of the FET Q1 and the other end of the feedback winding Nb, a resistor R2 connected between one end of the feedback winding Nb and a base of the transistor Q2, a resistor R3 and a capacitor C2 connected in parallel between the base and emitter of the transistor Q2, a resistor R4 connected in series between one end of the feedback winding Nb and the base of the transistor Q2, the diode D2 and a phototransistor PT on the light reception side of the photo coupler PC.
The operation of the switching power supply apparatus 1 illustrated in FIG. 7 is explained referring to the graph to FIG. 8 to indicate the change of the voltage and the current of each part of the switching power supply apparatus 1. In FIG. 8, Vgs denotes the voltage between the gate and source of the FET Q1, V1 denotes the voltage to be applied to the primary winding N1, I1 denotes the current flowing in the primary winding N1, Vds denotes the voltage between the drain and source of the, Vbe2 denotes the voltage between the base and emitter of the transistor Q2, Vb denotes the voltage generated in the feedback winding Nb, V2 denotes the voltage generated in the secondary winding N2 and I2 denotes the current flowing in the secondary winding N2. ON and OFF indicated at the upper part of the graph indicate the timing at which FET Q1 is turned from OFF to ON (hereinafter, referred to as "turn-ON"), and the timing at which the FET Q1 is turned from ON to OFF (hereinafter, referred to as "turn-OFF"), respectively.
Firstly, at the moment when the power source is turned ON at the start, the FET Q1 is in the OFF condition, and no current I1 flows in the primary winding N1, but current flows in the internal capacitance formed between the gate and the source of the FET Q1 through the starting resistor R1. The voltage Vgs between the gate and the source of the FET Q1 is increased, and the FET Q1 starts to turn ON at the time exceeding the threshold of the FET Q1. When the FET Q1 starts to turn ON, the voltage Vds between the drain and the source of the FET Q1 becomes approximately 0V, the input voltage is applied to the primary winding N1 of the transformer T, the current I1 starts to flow, and the voltages Vb and V2 are generated in the feedback winding Nb and the secondary winding N2. The current flows into the gate of FET Q1 from the feedback winding Nb through the resistor Rb and the capacitor C3. By the voltage Vb generated in the feedback winding Nb, the increase of the voltage Vgs between the gate and the source of the FET Q1 is accelerated, and FET Q1 is completely turned ON. The voltage V2 generated in the secondary winding N2 is the voltage reverse to the diode D1 for rectification, and no current I2 flows in the secondary winding N2.
When FET Q1 is turned ON and the voltage Vb of positive polarity is generated in the feedback winding Nb, the capacitor C2 is charged through the resistor R2, a resistor R4, a diode D4 and the photo-transistor PT which are described below, and the voltage across the capacitor C2, that is, the voltage Vbe2 between the base and the emitter of the transistor Q2 is increased. The charging speed (the time constant) is determined by the values of the resistors R2,R3,R4 and the capacitor C2 and the photo-transistor PT. When the voltage Vbe2 between the base and the emitter of the transistor Q2 is increased, and exceeds the forward voltage Vbe(on) 2 between the base and the emitter of the transistor Q2, the transistor Q2 is turned ON. When the transistor Q2 is turned ON, the voltage between the collector and the emitter of the transistor Q2, that is, the voltage Vgs between the gate and the source of FET Q1 is approximately 0V, and turns off the FET Q1.
When the FET Q1 starts to be turned off, the voltage V1 to be applied to the primary winding N1 is 0V, and the flowing current I1 is also 0. However, due to the magnetic energy accumulated in the transformer T by the current I1 flowing in the primary winding N1 when the FET Q1 is turned ON, a voltage of negative polarity is generated in the primary winding N1, the secondary winding N2, and the feedback winding Nb. A voltage of n-times (the turn ratio of the primary winding to the secondary winding) the voltage V2 of negative polarity generated in the secondary winding is generated in the primary winding. The current I2 generated by the voltage V2 of negative polarity generated in the secondary winding N2 flows through the diode D1 and is smoothed by the capacitor C4 and outputted. The voltage Vb of negative polarity generated in the feedback winding Nb rapidly absorbs the charge from the internal capacitance formed between the gate and the source of the FET Q1 through the capacitor C3 and the resistor Rb, and the FET Q1 is completely turned off. At the same time, the charge accumulated in the capacitor C2 is also absorbed through the resistor R2, a the reverse voltage is applied to the capacitor C2, and the capacitor C2 is further charged in the reverse direction, the voltage Vbe2 between the base and the emitter of the transistor Q2 is biased negative, and the transistor Q2 is turned OFF. The transistor Q2 is instantaneously turned ON only when it turns off the FET Q1.
The current I2 flowing in the secondary winding N2 when the FET Q1 is turned OFF, is gradually reduced as the magnetic energy from the transformer T is released, and finally becomes 0. When the current I2 flowing in the secondary winding N2 becomes 0, the voltages V2 and Vb generated in the secondary winding N2 and the feedback winding Nb tend to be attenuated in an oscillating manner with 0V on the boundary if they are left as they are. The voltage which is temporarily changed from the negative polarity to the positive polarity in the feedback winding Nb, is referred to as the "kick voltage". When the kick voltage is generated in the feedback winding Nb, the current flows from the feedback winding Nb into the internal capacitance formed between the gate and the source of the FET Q1 through the resistor Rb and the capacitor C3, and the voltage Vgs between the gate and the source of the FET Q1 is increased. When the kick voltage is not less than the prescribed value, the voltage Vgs between the gate and the source exceeds the threshold, and the FET Q1 is turned on. Because the starting resistor R1 is set to a large value, the current flowing through it is small, and it does not cause the FET Q1 to be turned on by the current flowing in the starting resistor R1 like starting. As the FET Q1 is turned on, the voltages V2 and Vb generated in the secondary winding N2 and the feedback winding Nb are forcibly increased to the positive polarity, and the oscillation of the voltage is forcibly terminated.
Subsequently, similar operation to that at starting is repeated, the FET Q1 is repeatedly turned on and turned off to be operated as the switching power supply apparatus.
The voltage stabilizing operation is finally described. In the voltage detection circuit 4, the output voltage is split by two resistors R6 and R7 for detection, and inputted in the shunt regulator Sr. The shunt regulator Sr compares the inputted voltage with the internal reference voltage, and causes a current to flow according to the difference.
When the load (not shown in the figure) to be connected to the switching power supply apparatus 1 is decreased, and the output voltage is increased, the voltage at the connection part of the resistor R6 to the resistor R7 is also increased, the input voltage to the shunt regulator Sr is increased to allow more current to flow. When the current flowing in the shunt regulator Sr is increased, the current flowing in the light-emitting diode PD of the photo coupler PC connected thereto in series is also increased, and the quantity of light emitted from the light-emitting diode PD is increased. When the quantity of light emitted from the light-emitting diode PD is increased, the current flowing in the photo-transistor PT of the photo coupler PC connected to the control circuit 5 is also increased. The current flowing in the photo-transistor PT is the current to charge the capacitor C2 together with the current flowing in the resistor R2 when the voltage Vb generated in the feedback winding Nb is of the positive polarity as described above, and when the current flowing in the photo-transistor PT is increased, the time to charge the capacitor C2 is shortened. As a result, the time until the transistor Q2 is turned ON is shortened, and the time until the FET Q1 is turned off, that is, the time while the FET Q1 is ON is shortened. When the time while the FET Q1 is ON is short, the magnetic energy accumulated in the transformer T is also smaller, the voltage V2 generated in the secondary winding N2 is also dropped, and the output voltage is reduced. Because the time while the FET Q1 is OFF is shortened proportional to the time while the FET Q1 is ON, the switching frequency of the switching power supply apparatus 1 is increased by the shortening of the time while the FET Q1 is ON and OFF.
On the contrary, when the load (not shown in the figure) to be connected to the switching power supply apparatus 1 is increased, and the output voltage drops, the current flowing in the photo-transistor PT of the photo coupler PC is decreased, the charging time of the capacitor C2 is increased, the time until the FET Q1 is turned off, that is, the time while the FET Q1 is ON becomes longer, the voltage V2 generated in the secondary winding N2 is increased, and the output voltage is increased. Because the time while the FET Q1 is ON is longer, the switching frequency of the switching power supply apparatus 1 is reduced. In this way, the voltage is stabilized in the switching power supply apparatus 1.
While the FET Q1 is turned off and while the FET Q1 is turned on, there exists a condition where the voltage is applied between the drain and the source of the FET Q1 and moreover, the current flows though the time is short. A loss in the FET Q1 is generated in this condition (hereinafter, referred to as the "switching loss"). Because the switching loss is generated whenever the FET Q1 is turned on and turned off, the magnitude of the switching loss affects the efficiency of the switching power supply apparatus 1. Also, because the total switching loss during the prescribed period is proportional to the switching frequency of the FET Q1, the switching frequency also affects the efficiency of the switching power supply apparatus 1.
To explain the mechanism of generation of the switching loss, FIGS. 9A and 9B indicate the time change of the voltage Vds between the drain and the source of the FET Q1 during the turn-OFF and the current I1 flowing therein on an expanded time scale. FIGS. 10A and 10B show the time change of the voltage Vds between the drain and the source of the FET Q1 during the turn-ON and the current I1 flowing therein, the current I2 flowing in the secondary winding N2, the voltage Vb generated in the feedback winding Nb, and the voltage Vgs between the gate and the source of the FET Q1 in the expanded time scale.
Firstly, during the turn-OFF, after the transistor Q2 is turned ON, a voltage of negative polarity is generated in the feedback winding Nb, the charge accumulated in the gate of the FET Q1 is absorbed through the capacitor C3 and the resistor Rb, and the gate voltage Vgs is rapidly reduced to turn OFF the FET Q1. However, as indicated in FIG. 9A, a certain time is required until the current flowing in the FET Q1 is completely 0 and the voltage Vds between the drain and the source is increased and stabilized. During this time, the voltage is applied between the drain and the source of the FET Q1 and the current flows, and the switching loss is generated. The hatched part in FIG. 9A is the part corresponding to the switching loss, and the area indicates the magnitude of the switching loss. The area of the hatched part is reduced so as to reduce the switching loss, and for this purpose, the turn-off speed of the FET Q1 is increased. This can be achieved by reducing the resistance of the resistor Rb as much as possible so as to easily allow current directed from the gate of the FET Q1 to the feedback winding Nb to flow. On the contrary, if the resistance of the resistor Rb is increased, the turn-off speed is reduced, the voltage is applied between the drain and the source of the FET Q1 as indicated in FIG. 9B, the current-flowing time is increased, and the area of the hatched part, that is, the switching loss is increased.
On the other hand, during the turn-on, as indicated in FIG. 10A, the operation is started from the time point when the current I2 flowing in the secondary winding N2 is 0. When the current I2 flowing in the secondary winding N2 is 0, the voltage V2 (not shown in the figure) generated in the secondary winding N2, the voltage Vb generated in the feedback winding Nb, and the voltage Vds between the drain and the source of the FET Q1 are attenuated in an oscillating manner as indicated by the dotted line, reaching to a certain value. The voltage Vb of the feedback winding Nb is temporarily changed from the negative polarity to the positive polarity and turned into the kick voltage, and the current flowing in the feedback winding Nb flows into the gate of the FET Q1 through the resistor Rb and the capacitor C3. When the voltage Vgs between the gate and the source of the FET Q1 exceeds the threshold Vth, the FET Q1 is turned on. When the turn-on speed of the FET Q1 is large, the current I1 starts to flow before the voltage Vds between the drain and the source of the FET Q1 has not sufficiently dropped. Because a certain time is required before the voltage between the drain and the source of the FET Q1 is 0V, the greater the voltage that is applied between the drain and the FET Q1 source of the, the sooner the FET Q1 is turned on, and the longer the current flows, and the time of generating the switching loss indicated by the hatching in FIG. 10A becomes longer. To reduce the switching loss, the turn-on time of the FET Q1 can be delayed to some degree, and for this purpose, the current from the feedback winding Nb to the gate of the FET Q1 through the resistor Rb and the capacitor C3 is difficult to cause to flow by increasing the resistance of the resistor Rb to some degree. FIG. 10B indicates the timing when the resistance of the resistor Rb is increased to some degree, and because the time that the voltage Vgs between the gate and the source of the FET Q1 reaches the threshold is long, the FET Q1 is turned on after the voltage Vds between the drain and the source of the FET Q1 has sufficiently dropped, the time of generating the switching loss is shortened, and the voltage Vds between the drain and the source of the FET Q1 is also dropped.
To reduce the switching loss during the turn-off, the resistance of the resistor Rb is required to be small, while, to reduce the switching loss during the turn-on, the resistance of the resistor Rb is required to be large. Thus, the resistance of the resistor Rb is in a conflicting relationship between the turn-on and the turn-off, and required to be set to an appropriate value in a balanced manner, and in any case, this has been a difficult problem in reducing the switching loss.
Further, as described above, the switching power supply apparatus of an RCC system is characterized in that the switching frequency is increased as the load is decreased, and there is a problem that the switching loss is increased for a particularly small load because the switching loss is proportional to the switching frequency.
The basic structure of the switching power supply apparatus illustrated in FIG. 11 is disclosed in Japanese Unexamined Patent Publication No. 8-80041. In FIG. 11, the same symbol is attached to the part same as or equivalent to the part in FIG. 7, and its explanation is omitted.
In the switching power supply apparatus 6 in FIG. 11, the difference from the switching power supply apparatus 1 in FIG. 7 is that the diode D3 and a resistor R8 which are connected to each other in series, are connected in parallel to the resistor Rb in the control circuit 7. The anode of the diode D3 is connected to the gate side of the FET Q1 and the cathode is connected toward one end side of the feedback winding Nb.
In such a construction, by setting the resistance of the resistor Rb to a large value, and setting the resistance of the resistor R8 to be smaller than the resistance of the resistor Rb, the charge accumulated in the gate of the FET Q1 by the parallel resistance of the resistors Rb and R8 (approximately agreed with the resistor R8 of substantially small resistance) is rapidly absorbed by the feedback winding Nb to increase the turn-off speed during the turn-off of the, while the gate voltage Vgs of the FET Q1 delays exceeding the threshold if the resistor Rb is set to a large resistance, and the turn-off timing is delayed during the turn-on of the FET Q1.
However, also in this case, the turn-on time is dependent only on the resistance of the resistor Rb, and the turn-on timing of the FET Q1 is delayed, that means, reduction of the switching frequency is limited. Further, the FET Q1 is required to be rapidly turned on after the FET Q1 is started to be turned ON, but it takes long before the turn-on time of the FET Q1 if the resistance of the resistor Rb is excessively increased, and the switching loss is increased all the more.
Thus, there is a need for a switching power supply apparatus capable of reducing the switching loss both during the turn-off and the turn-on of the switching element, and for suppressing the increase of the switching frequency during small loading conditions to reduce the switching loss.